A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...

At the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA) on the CPU side of things. The news was ...

This TechXchange examines various platforms the utilize the RISC-V instruction set and architecture. This includes boards and modules as well as chips. SiFive put one of its RISC-V designs on a ...

To some, an operating system is a burden or waste of resources, like those working on embedded systems and other low-power applications. To others it’s necessary, abstracting away hardware so that ...

The semiconductor industry increasingly needs more flexible and scalable processor architectures, driving the growing adoption of RISC-V. Originally developed at the University of California, Berkeley ...

When faced with an FPGA, some people might use it to visualize the Mandelbrot set. Others might use it to make CPUs. But what happens if you combine the two? [Michael Kohn] shows us what happens with ...

RISC-V Inside: DeepComputing recently announced the DC-ROMA RISC-V mainboard, a limited-edition platform providing a unique way to experiment with the RISC-V instruction set. The Chinese company ...